module top_module(
input a,
input b,
input c,
output out );
assign out = ~((~a)&(~b)&(~c));
endmodule
4-variable(1)
CD\AB
00
01
11
10
00
1
1
0
1
01
1
0
0
1
11
0
1
1
1
10
1
1
0
0
实现上面卡诺图所描述的电路,代码如下:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a & ~d | ~b & ~c | b & c & d | a & c & d;
endmodule
4-variable(2)
CD\AB
00
01
11
10
00
d
0
1
1
01
0
0
d
d
11
0
1
1
1
10
0
1
1
1
实现上面卡诺图所描述的电路,其中,无关项d可以根据化简需求自己制定为0或是1,代码如下:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a | (~a&~b&c);
endmodule
4-variable(3)
CD\AB
00
01
11
10
00
0
1
0
1
01
1
0
1
0
11
0
1
0
1
10
1
0
1
0
实现上面卡诺图所描述的电路,代码如下:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a & b & ~c & ~d | a & ~b & ~c & ~d |
~a & ~b & ~c & d | a & b & ~c & d |
~a & b & c & d | a & ~b & c & d |
~a & ~b & c & ~d | a & b & c & ~d;
endmodule